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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. mos integrated circuit pd16344 64-bit ac-pdp driver document no. s14575ej2v0ds00 (2nd edition) date published november 2000 ns cp(k) printed in japan data sheet 1999, 2000 the mark shows major revised points. description the pd16344 is a row driver for an ac plasma display panel (pdp) using high breakdown voltage cmos process. the pd16344 consists of a 64-bit bi-directional shift register, latch circuit and high breakdown voltage cmos driver section. the logic section operates on a 5-v power supply so that it can be connected directly to a gate array and microcomputer (cmos level input). the driver section provides high breakdown voltage output of 120 v and +400 ma, ? 150 ma. both the logic and driver sections are constructed by cmos, witch allows operation with low power consumption. features ? high voltage full cmos process ? high breakdown voltage, high current output (maximum rating: 120 v, +400 ma, ? 150 ma) ? 64-bit bi-directional shift register on chip ? data control by transfer clock (external) and latch ? high-speed data transfer capability (f clk = 12 mhz max.: when cascaded) ? wider operating ambient temperature (t a = ? 40 c to 85 c) ordering information part number package pd16344gf-3ba 100-pin plastic qfp(14 x 20)
data sheet s14575ej2v0ds 2 pd16344 1. block diagram (shift register: 64-bit) v dd2 v ss2 da dk o 1 v dd2 v ss2 da dk o 64 /oe /lblk /clr b sr: 64-bit shift register hblk le1 le2 a clk clr b a sr le1, le2 s 1 s 2 s 3 s 4 s 61 s 62 s 63 s 64 s 1 s 2 s 3 s 4 s 61 s 62 s 63 s 64 l 1 l 64 clk remark /xxx indicates active low signal.
data sheet s14575ej2v0ds 3 pd16344 2. pin configuration (top view) pd16344gf-3ba o 1 o 2 o 3 o 4 o 5 o 6 o 7 o 8 o 9 o 10 o 11 o 12 o 13 o 14 o 15 o 16 o 17 o 18 o 19 o 20 o 21 o 22 o 23 o 24 o 25 o 26 o 27 o 28 o 29 o 30 o 64 o 63 o 62 o 61 o 60 o 59 o 58 o 57 o 56 o 55 o 54 o 53 o 52 o 51 o 50 o 49 o 48 o 47 o 46 o 45 o 44 o 43 o 42 o 41 o 40 o 39 o 38 o 37 o 36 o 35 dk1 da1 v ss2 v dd2 /oe hblk /lblk /clr a v dd1 b le1 clk v ss1 r,/l le2 v dd2 v ss2 da2 dk2 o 31 o 32 dk1 da1 da1 v ss2 v dd2 v sub v sub v dd1 v ss1 v sub v sub v dd2 v ss2 da2 da2 dk2 o 33 o 34 80 1 30 51 81 100 31 50 caution be sure to use all of the v dd1 , v dd2 , v ss1 , and v ss2 pins. use v ss1 , v ss2 , and v sub at the same potential .
data sheet s14575ej2v0ds 4 pd16344 3. pin functions pin symbol pin name pin number description hblk high blanking input 45 all output = h, when hblk = h le1, le2 latch strobe input 35, 39 l = through, h = data preservation le1: latch of odd register le2: latch of even register a left data input 42 b right data input 40 when r,/l = l: a: input b: output when r,/l = h: a: output b: input clk clock input 38 shift performed on a rising edge /oe enable input 46 l = all output, high-impedance /lblk low blanking input 44 all output = l, when /lblk = l r,/l shift control input 36 l = left shift mode a o 1 ? o 64 b h = right shift mode b o 64 ? o 1 a /clr register clear 43 l = all shift register data cleared (l level clear) o 1 to o 64 high withstand voltage output 1 to 30, 51 to 82, 99, 100, 110 v, +300 ma, ? 100 ma da1 diode source 1 49, 84, 85 diode source pin for o 1 to o 32 dk1 diode sink 1 50, 83 diode sink pin for o 1 to o 32 da2 diode source 2 32, 96, 97 diode source pin for o 33 to o 64 dk2 diode sink 2 31, 98 diode sink pin for o 33 to o 64 v dd1 logic section power supply 41, 90 5 v 10 % v dd2 driver section power supply 34, 47, 87, 94 30 to 110 v v ss1 logic ground 37, 91 connected to system gnd v ss2 driver ground 33, 48, 86, 95 connected to system gnd v sub substrate ground 88, 89, 92, 93 connected to system gnd
data sheet s14575ej2v0ds 5 m m m m pd16344 4. truth table shift register section input output r,/l clk a b /clr shift register l - output note1 h left shift operation performed lh or l input output h hold h - output note2 h right shift operation performed h h or l output input hhold l all registers = l notes 1. on the rising edge of the clock, the data of s 63 is shifted to s 64 , and data is output from b. 2. on the rising edge of the clock, the data of s 2 is shifted to s 1 , and data is output from a. latch section le operation (l n ) h holds and outputs data immediately before le becomes h. l outputs shift register data. driver section a (b) hblk /lblk /oe /clr driver output state hhh all driver output: h lh all driver output: l note l all driver output: high impedance llhhhh hlhhhl lhhlh note the capacity of the nch transistor decreases to about 1/4 of the normal state for a certain period of time at the falling edge of /lblk. refer to switching characteristics waveform on 8. electrical specifications. remark : h or l, h: high level, l: low level
data sheet s14575ej2v0ds 6 pd16344 5. timing chart (r,/l =?l?, when left shift mode) 1 clk a (b) /clr le1,2 hblk /lblk /oe s 1 (s 64 ) s 2 (s 63 ) s 3 (s 62 ) s 4 (s 61 ) s 5 (s 60 ) s 6 (s 59 ) s 63 (s 2 ) s 64 (s 1 ) o 1 (o 64 ) o 2 (o 63 ) o 3 (o 62 ) o 4 (o 61 ) o 63 (o 2 ) o 64 (o 1 ) b (a) 2345678 636465666768697071 remark in the parentheses: when r,/l=h
data sheet s14575ej2v0ds 7 pd16344 6. electrical specifications absolute maximum ratings (t a = 25 c, v ss1 = v ss2 = 0 v) parameter symbol ratings unit logic section supply voltage v dd1 ? 0.5 to +6.0 v driver section supply voltage v dd2 ? 0.5 to +120 v logic section input voltage v i ? 0.5 to v dd1 + 0.5 v driver section output current i o +400, ? 150 note ma diode peak forward current i fm 450 ma allowed package loss p d 1000 mw operating ambient temperature t a ? 40 to +85 c storage temperature t stg ? 65 to +150 c note simultaneous operation can be performed with up to 4 outputs. caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. recommended operation ranges (t a = ? ? ? ? 40 to +85 c, v ss1 = v ss2 = 0 v) parameter symbol conditions min. typ. max. unit logic section supply voltage v dd1 4.5 5.0 5.5 v driver section supply voltage v dd2 30 110 v high-level input voltage v ih 0.7 v dd1 v dd1 v low-level input voltage v il 0 0.2 v dd1 v i oh ? 100 ma i ol1 +300 ma driver output current i ol2 low capacity note (+75) ma i foh ? 400 ma diode forward current i fol +400 ma note the period of 560 ns max. from the falling edge of /lblk. the value enclosed in parentheses is a reference value.
data sheet s14575ej2v0ds 8 pd16344 electrical characteristics (t a = 25 c, v dd1 = 4.5 to 5.5 v, v dd2 = 110 v, v ss1 = v ss2 = 0 v) parameter symbol conditions min. typ. max. unit high-level output voltage v oh1 logic, i oh = ? 1.0 ma 0.9 v dd1 v dd1 v low-level output voltage v ol1 logic, i ol = 1.0 ma 0 0.1 v dd1 v high-level output voltage v oh2 o 1 to o 64 , i oh = ? 60 ma 90 100 v v ol21 o 1 to o 64 , i ol = 200 ma 4 8 v low-level output voltage v ol22 low capacity note1 , i ol = 50 ma (4) (8) v high-level output voltage v ohd o 1 to o 64 , i oh = ? 400 ma note2 , da = 110 v 103 105 v low-level output voltage v old o 1 to o 64 , i ol = 400 ma note2 , dk = 0 v 57v input leakage current i il v i = v dd1 or v ss1 1.0 a high-level input voltage v ih 0.7 v dd1 v low-level input voltage v il 0.2 v dd1 v i dd11 logic, t a = ? 40 to +85 c 500 a i dd11 logic, t a = 25 c 300 a i dd21 driver, t a = ? 40 to +85 c 1000 a static current consumption i dd21 driver, t a = 25 c 100 a notes 1. the period of 560 ns max. from the falling edge of /lblk. the value enclosed in parentheses is a reference value. 2. the current characteristic of the diode built into the output section is indicated.
data sheet s14575ej2v0ds 9 pd16344 switching characteristics (t a = 25 c, v dd1 = 4.5 to 5.5 v, v dd2 = 110 v, logic c l = 15 pf, driver c l = 50 pf) parameter symbol conditions min. typ. max. unit t phl1 70 ns t plh1 clk a, b 70 ns t phl2 /clr a, b 70 ns t phl3 160 ns t plh3 clk o 1 to o 64 160 ns t phl4 160 ns t plh4 le o 1 to o 64 160 ns t phl5 160 ns t plh5 hblk o 1 to o 64 160 ns t phl6 200 ns t plh6 /lblk o 1 to o 64 200 ns t phz 300 ns t pzh 160 ns t pzl 160 ns propagation delay time t plz /oe o 1 to o 64 r l = 20 k ? 300 ns output rising time t tlh o 1 to o 64 150 ns t thl1 o 1 to o 64 100 ns output falling time t thl2 low capacity note1 400 ns output nch low-driver capability period t la from the falling edge of /lblk (280) note2 (560) note2 ns data intake, duty = 50% 15 mhz clock frequency f clk cascade connection, duty = 50% 12 mhz input capacity c i 15 pf notes 1. the period of 560 ns max. from the falling edge of /lblk. 2. the value enclosed in parentheses is a reference value. timing requirements (t a = ? ? ? ? 40 to +85 c, v dd1 = 4.5 to 5.5 v, v ss1 = v ss2 = 0 v) parameter symbol conditions min. typ. max. unit clock pulse width pw clk(h) , pw clk(l) 30 ns latch enable pulse width pw le 30 ns pw hblk 300 ns blank pulse width pw /lblk 600 ns clear pulse width pw /clr 30 ns data setup time t setup 10 ns data hold time t hold 10 ns clock latch time t clk-le clk le 30 ns
data sheet s14575ej2v0ds 10 pd16344 switching characteristics waveform (1/3) 1/f clk pw clk (h) t setup t hold t phl1 t phl3 t phl2 t thl1 t plh3 t tlh t plh1 pw clk (l) v dd1 v ss1 v dd1 v ss1 v oh1 v ol1 v dd1 v ss1 v oh1 v ol1 v oh2 v ol2 50% 50% 50% 50% 50% 90% 10% 10% 90% 50% 50% 50% 50% clk a/b (input) b/a (output) o n /clr b/a (output)
data sheet s14575ej2v0ds 11 pd16344 switching characteristics waveform (2/3) 50% 50% 50% 50% 50% 90% 90% 90% 10% 10% 10% 10% t clk-le t phl4 t plh4 pw hblk t plh5 50% 50% pw /lblk t phl6 t thl2 t la t plh6 t phl5 pw le v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 v dd1 v oh2 v ol2 v oh2 v ol2 v oh2 v ol2 v oh2 v ol2 clk le hblk /lblk o n o n o n o n
data sheet s14575ej2v0ds 12 pd16344 switching characteristics waveform (3/3) 50% 10% /oe o n o n 10% 90% 90% t plz t pzl t phz t pzh 50% v dd1 v ss1 v oh2 v ol2 v oh2 v ol2
data sheet s14575ej2v0ds 13 pd16344 8. package drawing 80 81 50 100 1 31 30 51 s s 100 pin plastic qfp (14x20) item millimeters d f g i j 0.8 0.6 0.65 (t.p.) 0.15 17.2 0.2 q s100gf-65-3ba-4 note each lead centerline is located within 0.15 mm of its true position (t.p.) at maximum material condition. c 14.0 0.2 m 0.17 0.125 0.075 a 23.2 0.2 h 0.32 0.08 l 0.8 0.2 n 0.10 p 2.7 s 2.825 0.175 + 0.08 ? 0.07 b 20.0 0.2 k 1.6 0.2 r5 5 m n detail of lead end i j f g h q r p k m l a b cd s
data sheet s14575ej2v0ds 14 pd16344 9. soldering conditions solder the product under the following recommended conditions. for details of the recommended soldering conditions, refer to information document semiconductor device mounting technology manual (c10535e). for soldering methods and soldering conditions other than those recommended, please contact one of our sales representatives. surface mount type pd16344gf-3ba: 100-pin plastic qfp(14 x 20) soldering method soldering condition symbol of recommended soldering condition infrared reflow package peak temperature: 235 c, time: 30 seconds max. (210 c min.), number of times: 3 max., max day: 7 days (need 10 hours with 125 c pre- beak after limited day) products other than in hear-resistant trays (such as those packaged in a magazine, taping, or non-thermal-resistant tray) cannot be baked in their package. ir35-207-3 vps package peak temperature: 215 c, time: 40 seconds max. (200 c min.), number of times: 3 max., max day: 7 days (need 10 hours with 125 c pre- beak after limited day) products other than in hear-resistant trays (such as those packaged in a magazine, taping, or non-thermal-resistant tray) cannot be baked in their package. vp15-207-3 partial heating pin temperature: 300 c max., time: 3seconds max. (per side of device) ? caution do not use two or more soldering methods in combination (except the partial heating method).
data sheet s14575ej2v0ds 15 pd16344 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
pd16344 reference documents nec semiconductor device reliability/quality control system (c10983e) quality grades to nec ? s semiconductor devices (c11531e) m8e 00. 4 the information in this document is current as of november, 2000. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the p ossibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": com puters, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above). ? ? ? ? ? ?

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